Memory chips comprise an array of memory cells which are interconnected by bit lines and word lines. The word lines and bit lines are used to read and write binary values to each of the memory cells, with each of the memory cells representing a bit of information. Since each memory cell represents a bit of information and may be connected to other circuitry, it is desirable that the electrical and operational characteristics of all memory cells be consistent.
A sense amplifier is an element in the memory chip circuitry. Specifically, the sense amplifier senses low power signals from a bitline that represents a data bit (1 or 0) stored in a memory cell, and amplifies a small voltage swing to recognizable logic levels so that the data can be interpreted properly by logic outside of the memory. Issues can arise in a multiple path sense amplifier because they require either calibration or sizable devices to mitigate inherent device mismatch. Specifically, a mismatch between the p-type and n-type devices creates an offset between Vbit and Vref, which causes issues because the data bit resistance is equal to a reference resistance, with the reference resistance point being shifted due to the offset between Vbit and Vref.
In order to minimize the offset, larger size devices are implemented to minimize the mismatch. However, these larger devices can slow down the Vref settling time and prolong the Vbit sensing time significantly. Further, as devices continue to decrease in size, the space needed for these larger devices is not available.